Field of the Invention
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated circuit having a programmable element, in the case of which an electrical interconnect resistance can be varied by programming, and having an evaluation circuit, connected to the programmable element, for the evaluation of the electrical interconnect resistance. The invention also pertains to a method for operating the integrated circuit.
Integrated circuits often have redundancy circuits for repairing defective circuit sections. In the case of integrated memory circuits, in particular these may be, for example, regular word lines and bit lines with defective memory cells which are replaced by redundant word lines and bit lines, respectively. To that end, the integrated circuit is tested in a test operation and the redundant elements are subsequently programmed. To that end, a redundancy circuit has programmable elements, for example in the form of so-called fuses, which serve, for the case of repairing word lines or bit lines, for storing the address of a line to be replaced.
Such programmable elements are embodied for example in the form of electrically programmable fuses or laser fuses which have an electrical interconnect resistance which can be permanently varied by the programming. Electrically programmable fuses are programmable for example at the end of the integrated circuit fabrication process by application of a so-called blowing voltage. Laser fuses are generally programmed by bombardment with a laser beam.
A programmable element in the form of a fuse has an existing low-resistance electrical connection which is, as it were, severed by the programming (high-resistance interconnect resistance). An electrically programmable element in the form of a so-called antifuse has, in the non-programmed state, an interruption (high-resistance interconnect resistance) in a voltage path, which is put into a low-resistance state by a programming.
In order to read out and evaluate the state of a programmable element or the electrical interconnect resistance thereof, an evaluation circuit for reading out and evaluating the electrical interconnect resistance of the element is generally connected to the relevant programmable element. Such an evaluation circuit usually contains a read-out transistor, connected to the programmable element, and a volatile memory element in the form of a so-called fuse latch, connected to the read-out transistor.
During the evaluation of the state of the programmable element, the problem generally arises that the regions of the interconnect resistance which are to be used to evaluate the programmable element as programmed or as non-programmed are occasionally subjected to technological fluctuations. A programmable fuse or antifuse has a silicon nitride layer, for example, which is arranged between a metalization plane and a contact and can be varied in its electrical conductivity in accordance with the programming. With a construction of this type, technological fluctuations arise for example in the form of production-dictated variation of the thickness of the silicon nitride layer and/or a varying configuration of the electrodes above the silicon nitride layer. In order to be able to carry out an evaluation of the state of the programmable element, generally a respective resistance limit value is defined for the programmed state and non-programmed state. In this case, deviations from the respective resistance limit value on account of technical fluctuations can have the result that the state of the programmable elements is no longer evaluated entirely satisfactorily and reliably.
It is accordingly an object of the invention to provide an integrated circuit and an operating method which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provide for an integrated circuit having a programmable element wherein a state of the programmable element can be read out and evaluated reliably to a large extent. Furthermore, it is an object of the present invention to provide a method for operating such an integrated circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
a programmable element having an electrical interconnect resistance variable by programming;
an evaluation circuit, connected to the programmable element, for evaluating the electrical interconnect resistance of the programmable element; and
a trimming circuit, connected to the evaluation circuit, for variably setting an operating point of the evaluation circuit in an operation of the integrated circuit.
With the above and other objects in view there is also provided, in accordance with the invention, a method of operating the above-outlined integrated circuit. The method comprises the following steps:
reading out an electrical interconnect resistance of the programmable element and evaluating the electrical interconnect resistance with the evaluation circuit; and
adjusting an operating point of the evaluation circuit with the trimming circuit in dependence on the electrical interconnect resistance obtained in the reading out step.
In other words, the integrated circuit according to the invention has a trimming circuit, connected to the evaluation circuit for the evaluation of the electrical interconnect resistance of the programmable element, the trimming circuit serving for the variable setting of an operating point of the evaluation circuit in an operation of the integrated circuit. As a result, to a certain extent, it is possible to compensate for technological fluctuations of the electrical interconnect resistance in the programmed state or in the non-programmed state of the programmable element, in particular during a test operation.
To that end, in accordance with the method according to the invention, for example in a test operation of the integrated circuit, the electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With the trimming circuit, an operating point of the evaluation circuit is adjusted in a manner dependent on the read-out value of the electrical interconnect resistance. Consequently, the operating ranges of the programmable element and of the evaluation circuit can be coordinated with one another in such a way that a largely reliable read-out and evaluation of the programmable element is made possible in a later normal operation of the integrated circuit.
In accordance with an added feature of the invention, the evaluation circuit has a read-out transistor, connected to the programmable element. In this case, the trimming circuit serves for the variable setting of a control voltage at a control terminal of the read-out transistor. With the variable setting of the control voltage at the control terminal of the read-out transistor, the operating range thereof can be set and adapted with regard to the state of the programmable element. For this purpose, the trimming circuit is provided in particular for controlling a voltage generator, connected to the control terminal of the read-out transistor, and is connected thereto.
In accordance with an additional feature of the invention, the evaluation circuit has a terminal for the external read-out of the electrical interconnect resistance of the programmable element. As a result, the state of the programmable element can be read out toward the outside, for example, in a test operation. The trimming circuit, which is externally programmable, can then be adjusted in a manner dependent on the read-out state of the programmable element.
In accordance with an advantageous embodiment, this process is performed by a self-test unit for carrying out a test operation. In this case, the self-test unit automatically performs the evaluation of the electrical interconnect resistance of the programmable element and the setting of the operating point of the evaluation circuit in a manner dependent on the evaluation.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a integrated circuit having a programmable element and method for operating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.